Portrait
Jana Toljaga
PhD student
Inria Saclay & Télécom SudParis, IP Paris
About Me

I am a PhD candidate in operating systems in Benagil team co-hosted by Inria and Télécom SudParis (Institut Polytechnique de Paris). This PhD thesis is directed by Gaël Thomas and co-supervised by Nicolas Derumigny and Mathieu Bacou.

I specialize in storage and memory systems, with an interest in virtualization as a mechanism for rethinking conventional system-stack abstractions. My research investigates how virtualization can enable access to system features to deliver better performance and reduce engineering costs of memory and storage intensive applications. In this context, my PhD research began with designing libVoliMem, a micro-VM able to turn any process into a virtual machine with a customizable minimal kernel. So far, I have participated in multiple projects that emerged from libVoliMem to improve storage and memory management, develop hardware optimized parallel algorithms and ensure security.

My main contribution is VoliStorM, a crash-consistent I/O cache with two kernels instead of two caches. VoliStorM targets low-latency storage devices such as persistent memory and NVMe, using latency-oriented kernel inside libVoliMem. I implemented a crash-consistent storage stack that cooperates with Linux while reducing the overheads of traditional storage systems. This work was published at SOSP 2026.

Education
  • Inria Saclay & Télécom SudParis, IP Paris
    Inria Saclay & Télécom SudParis, IP Paris, France
    Sep. 2023 - present
    Benagil team, Samovar laboratory
    Ph.D. Student in computer science
  • Institut Polytechnique de Paris
    Institut Polytechnique de Paris, France
    Sep. 2022 - Sep. 2023
    MSc in Parallel and Distributed Systems
  • School of Electrical Engineering, University of Belgrade
    School of Electrical Engineering, University of Belgrade, Serbia
    Oct. 2018 - Jul. 2022
    Software Engineering
Experience
  • Inria Saclay & Télécom SudParis, IP Paris
    Inria Saclay & Télécom SudParis, IP Paris, France
    Sep. 2023 - present
    Ph.D. Candidate
  • École polytechnique (l'X)
    École polytechnique (l'X), France
    Sep. 2025 - Jan. 2026
    Teaching Assistant
  • École polytechnique fédérale de Lausanne (EPFL)
    École polytechnique fédérale de Lausanne (EPFL), Switzerland
    Jul. 2022 - Sep. 2022
    Research Intern
  • Microsoft
    Microsoft, Serbia
    Feb. 2022 - May 2022
    Software Engineer Intern
Selected Publications (view all )
VoliStorM: A Crash-Consistent I/O Cache with Two Kernels Instead of Two Caches
VoliStorM: A Crash-Consistent I/O Cache with Two Kernels Instead of Two Caches

Jana Toljaga, Nicolas Derumigny, Tara Aggoun, Mathieu Bacou, Gaël Thomas

The 32nd Symposium on Operating Systems Principles (SOSP 2026) 2026

A crash-consistent I/O cache is essential to ensure data integrity while optimizing performance. However, a general-purpose kernel fails to ensure integrity efficiently because of the high cost of synchronizing I/O... Read more

VoliStorM: A Crash-Consistent I/O Cache with Two Kernels Instead of Two Caches

Jana Toljaga, Nicolas Derumigny, Tara Aggoun, Mathieu Bacou, Gaël Thomas

The 32nd Symposium on Operating Systems Principles (SOSP 2026) 2026

A crash-consistent I/O cache is essential to ensure data integrity while optimizing performance. However, a general-purpose kernel fails to ensure integrity efficiently because of the high cost of synchronizing I/O... Read more

Privagic: automatic code partitioning with explicit secure typing
Privagic: automatic code partitioning with explicit secure typing

Subashiny Tanigassalame, Yohan Pipereau, Adam Chader, Jana Toljaga, Gaël Thomas

Proceedings of the 25th International Middleware Conference (Middleware 2024) 2024

Partitioning a multi-threaded application between a secure and a non-secure memory zone remains a challenge. The current tools rely on data flow analysis techniques, which are unable to handle multi-threaded... Read more

Privagic: automatic code partitioning with explicit secure typing

Subashiny Tanigassalame, Yohan Pipereau, Adam Chader, Jana Toljaga, Gaël Thomas

Proceedings of the 25th International Middleware Conference (Middleware 2024) 2024

Partitioning a multi-threaded application between a secure and a non-secure memory zone remains a challenge. The current tools rely on data flow analysis techniques, which are unable to handle multi-threaded... Read more

All publications
News
2026
Presented VoliStorM, a crash-consistent I/O cache with two kernels instead of two caches, with a talk and a poster at SOSP 2026 in Prague, Czechia.
Sep
2025
Gave a talk on leveraging a userland page table towards transparent usage of persistent memory at Compas 2025 in Bordeaux, France.
Jun
Invited talk on VolipMem, a system-level PMEM runtime, at Per3S 2025 in Paris, France.
May
2024
Presented a poster "Userland Page Table: A Key for Transparent Persistent Memory" at Middleware 2024 in Hong Kong.
Dec
Presented a poster on transparent usage of persistent memory at the EuroSys 2024 Doctoral Workshop in Athens, Greece.
Apr